Nvidia’s
Blackwell GPU architecture, launched in 2024 and deployed at scale through
the H200 and B100 series chips, delivered performance improvements over the
previous Hopper generation that the company characterised as the largest
generational leap in its GPU history. For training large language models, the
benchmark improvements were substantial: throughput on transformer training
workloads approximately doubled in comparable system configurations, and the
combination of improved memory bandwidth, enhanced tensor core performance,
and NVLink interconnect improvements reduced the time and cost required to
train frontier AI models significantly. For an industry in which training
compute is one of the primary constraints on capability advancement, a
doubling of training throughput at comparable cost represents a significant
acceleration in the pace at which new frontier models can be developed and
improved.

The AI chip market in 2025 is more strategically significant than
any previous semiconductor market segment in the history of the technology
industry. The chips that train and run AI models are not merely components in
a supply chain; they are the physical infrastructure on which the AI
capabilities that are reshaping economies, militaries, and societies depend.
Control over this infrastructure, including who designs the chips, who
manufactures them, and who has access to them, has become a central concern
of technology policy, export control, and geopolitical competition in a way
that no previous chip market has approached. Understanding what Blackwell
achieves technically and what its implications are requires context about
both the competitive landscape and the geopolitical dynamics that are shaping
access to advanced AI computing infrastructure.

Blackwell Architecture: What Changes

The Blackwell architecture’s most significant technical advances
over its Hopper predecessor are in the areas most relevant to large language
model training and inference. The second-generation transformer engine,
optimised for the attention mechanism calculations that dominate compute in
transformer-based models, delivers substantially higher throughput on these
calculations than Hopper hardware. The enhanced NVLink 5 interconnect enables
faster communication between GPUs in multi-chip training configurations,
reducing the communication overhead that becomes a binding constraint in very
large training runs involving thousands of chips. The chip’s support for FP4
and FP8 precision training modes, in addition to the FP16 and BF16 modes
supported by previous generations, enables training runs that use lower
precision arithmetic to reduce memory requirements and increase throughput at
acceptable accuracy costs.

The Blackwell-based DGX B200 system, Nvidia’s flagship AI training
platform, combines eight B200 GPUs with NVLink switching into a system
delivering AI training performance that would have required a significant
fraction of the world’s GPU capacity in 2020. The economics of frontier AI
training have shifted accordingly: what required a purpose-built data centre
three years ago can now be accomplished in a single rack, reducing the
infrastructure overhead of training experiments and enabling more rapid
iteration on model architectures and training approaches. This
democratisation of frontier training capability is relative rather than
absolute, since DGX B200 systems list at prices well above a million dollars
per unit, but it meaningfully changes the infrastructure requirements for
serious AI development.

Competition and the AMD Challenge

AMD’s MI300X, which provided the most credible competition to
Nvidia’s Hopper generation, has shown strong performance particularly for
inference workloads where its larger high-bandwidth memory capacity reduces
the need for data transfers that limit throughput on large models. AMD’s
MI300X found significant customer adoption at cloud providers including
Microsoft Azure and Oracle Cloud Infrastructure, demonstrating that the
market for AI accelerator chips is not entirely captured by Nvidia despite
its dominant position. The MI350 series, announced to compete with Blackwell,
claims to close the performance gap on training workloads while maintaining
or extending the memory capacity advantage on inference.

The competitive dynamics between Nvidia and AMD in AI chips are
shaped by more than technical performance. Nvidia’s CUDA software ecosystem,
which has been developed over fifteen years and is deeply embedded in the AI
research and development workflow, represents a switching cost that pure
hardware performance comparisons underestimate. Most AI frameworks, optimised
libraries, and development tools are designed primarily for CUDA, meaning
that AMD hardware, even when competitive on raw performance, requires
additional software engineering investment that many organisations are
reluctant to make. The Nvidia developer
platform continues to invest heavily in this ecosystem advantage,
making competitive response from AMD a software challenge as much as a
hardware one.

Geopolitical Dimensions

The AI chip market cannot be understood without engaging with the
export control framework that the US government has imposed on advanced AI
semiconductor exports to China. US restrictions on the export of Nvidia’s
most capable chips, including the H100 and subsequent generations, have been
a central element of US technology policy toward China since October 2022,
and they directly affect the competitive dynamics of AI development between
US and Chinese organisations. Nvidia has developed China-specific product
variants that comply with export restrictions while providing less capable AI
training performance, but the gap between what US AI developers can access
and what their Chinese counterparts can legally import has become a
significant factor in the international AI capability race. The policy
implications of this gap, including whether it is slowing Chinese AI
development at a meaningful rate or primarily redirecting investment toward
domestic chip development, are contested among researchers and policymakers
monitoring the competitive dynamics.

What This Means for You

The performance advances in Blackwell and its successors translate
into the AI capabilities available to you through consumer and enterprise AI
products, because the speed at which AI companies can train and improve their
models depends directly on the performance of the underlying hardware.
Faster, more efficient chips enable more frequent model updates, larger
training runs, and the development of new model architectures that improve
capabilities. The geopolitical dimensions of AI chip supply are relevant to
you in ways that are less direct but potentially more significant: the
regulatory framework governing which countries and organisations can access
the most capable AI chips is one of the primary levers through which
governments are attempting to shape the trajectory of AI development, and its
effects on AI capability distribution will influence who benefits from AI
advances over the coming decade. For related analysis, see our coverage of
frontier
AI capability races and AI
infrastructure energy demands.

The environmental implications of Blackwell’s performance
improvements deserve acknowledgment alongside their commercial significance.
More efficient hardware reduces energy cost per unit of AI capability, a
genuine benefit relative to achieving equivalent capability on less efficient
hardware. However, efficiency improvements in AI hardware historically
increase total energy consumption rather than reducing it, through the
dynamic known as the Jevons paradox: lower cost per training run enables
larger, more frequent training runs consuming more total energy. The AI
industry’s aggregate energy demand grows with each generation of more
efficient hardware rather than declining, because improved efficiency enables
scale expansion that outpaces the efficiency gain. Realising the
environmental potential of hardware improvements requires governance
constraining total AI energy consumption, not merely celebrating per-unit
efficiency. The IEA data centre
efficiency report provides authoritative analysis of how hardware
efficiency and total consumption relate in the current AI infrastructure
expansion.

About the Author

Stuart Kerr is a technology correspondent at LiveAIWire, covering
artificial intelligence, digital innovation, and the social impact of
emerging technologies. Follow LiveAIWire for daily analysis at liveaiwire.com.